1. Field of the Invention
The invention relates to a semiconductor device.
2. Description of Related Art
Japanese Patent Application Publication No. 2011-86746 (JP 2011-86746 A) describes a semiconductor device in which a gate pad is formed in a non-active region. In this semiconductor device, an element region and a termination region are formed in an active region. A plurality of linear trench gate electrodes are formed in the element region, and a plurality of termination trenches that encircle the plurality of trench gate electrodes are formed in the termination region. That is, the gate pad is arranged on an outer portion of the termination trench that is farthest to the outside. A p-type floating diffusion layer is formed on a bottom portion of gate trenches and a bottom portion of the termination trenches. The p-type floating diffusion layer is surrounded by an n-type drift region. In this semiconductor device, voltage resistance is retained by a PN junction of the p-type floating diffusion layer and the n-type drift diode formed on the bottom portion of the trenches, and a PN junction of a p-type body region and an n-type drift region.
With the semiconductor device described in JP 2011-86746 A, a gate pad is arranged to an outside of a voltage-resistance retaining structure formed in the termination region. That is, a gate pad is arranged to the outside of the voltage-resistance retaining structure. Therefore, when the voltage applied to the semiconductor device increases, high voltage is applied to the gate pad when there is a reverse bias, so the gate pad may become damaged.